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Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 9. VL1 and VL2 (Read/Write)
BIT
RESET
STATE
BIT VALUE
D15
X
X
D14
X
X
D13
X
X
D12
X
X
D11
0
MSB
D10
0
—
D9
0
—
D8
0
—
D7
0
—
D6
0
—
D5
0
—
D4
0
—
D3
0
—
D2
0
—
D1
0
—
D0
0
LSB
X = Don’t care.
Table 10. HCFG (Read/Write)
BIT NAME
X
CH2OCM1
CH2OCM0
CH1OCM1
CH1OCM0
X
DATA BIT
D15–D12
D11
D10
D9
D8
D7
RESET STATE
X
0
0
0
0
X
FUNCTION
Don’t care.
Maximum GATE2 voltage control bits.
Maximum GATE1 voltage control bits.
Don’t care.
ADC monitor bit. Set to 1 to load ADC results into the FIFO. Set to 0 to not
load any ADC results into the FIFO. The value of ADCMON does NOT
ADCMON
D6
0
affect whether the results from any particular ADC conversion are
checked against ALARM limits or examined for changes to the
V DAC(CODE) equations.
CKSEL1
CKSEL0
ADCREF1
ADCREF0
DACREF1
DACREF0
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
Clock mode and CNVST configuration bits.
ADC reference select bits.
DAC reference select bits.
HCFG (Read/Write)
Select each channel’s maximum GATE voltage, clock
mode, ADC monitoring, DAC and ADC reference
modes by setting bits D11–D0 in the hardware configu-
ration register. Set the command byte to 38h to write to
the hardware configuration register. Set the command
byte to B8h to read from the hardware configuration
register. Bits D15 –D12 are don ’t care. Set the
CH2OCM1/0 bits, D11 and D10, to determine the maxi-
mum positive GATE2 output voltage. Set the
CH1OCM1/0 bits, D9 and D8, to determine the maxi-
mum positive GATE1 output voltage. See Table 10.
Set the ADCMON bit, D6, to 1 to load the ADC results
into the FIFO. Set ADCMON to 0 to not load ADC
results into the FIFO. Set the CKSEL1/0 bits, D5 and
D4, to determine the conversion and acquisition timing
clock modes. See Table 10b. Also, see the Internally
Timed Acquisitions and Conversions and the Externally
Timed Acquisitions and Conversions sections. Set the
ADCREF1/0 bits, D3 and D2, to determine the ADC ref-
erence source. See Table 10c. Set the DACREF1/0 bits,
D1 and D0, to determine the DAC reference source.
See Table 10d.
SCFG (Read/Write)
Write to the software configuration register to determine
whether a V DAC(CODE) calculation value is loaded to
the DAC input register or DAC input and output regis-
ter. This register also sets the control modes for the K
parameter and temperature lookup values in the
V DAC(CODE) calculation. Set the command byte to 3Ah
to write to the software configuration register. Set the
command byte to BAh to read from the software config-
uration register.
______________________________________________________________________________________
35
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